Honored Contributor
Honored ContributorA std_logic vector is really just a single bit.
std_logic_vector and unsigned are both an array of std_logic. As they are closely related types but not the same type, a type conversion is required, as you demonstrated. The ONLY difference between unsigned and std_logic_vector is that they are declared separately. They are named differently for abstraction and understanding purposes. At the end of the day, they are synthesized into the same thing. Unsigned/signed have a package of useful function in the form of numeric_std that does arithmatic on them. Std_logic_vector does not have an IEEE package for arithmatic (until VHDL 2008). --- Quote Start --- But now, I am ok with the fact that he did not get an error, but anyway it is always better to be coherent between signal and use unsigned only if it is needed. --- Quote End --- So whats wrong with leaving it as unsigned?
