VHDL and Megafunctions

Thank you for responding.

At the bottom are the three files the the wizard generated. Where should

they be placed. Sorry for being lame but I have still not got this to work.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity PCIad is port(

);

end PCIad;

architecture archPCIad of PCIad is

begin

end archPCIad;

-------------------------------------------------------

component ALT_PLL

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

--------------------------------------------------------

FUNCTION ALT_PLL (areset, inclk0)

RETURNS (c0, locked);

--------------------------------------------------------

ALT_PLL_inst : ALT_PLL PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

--------------------------------------------------------

It should look like this

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity PCIad is port(

areset_sig: in STD_LOGIC;

inclk0_sig: in STD_LOGIC;

c0_sig: out STD_LOGIC;

locked_sig: out STD_LOGIC

);

end PCIad;

architecture archPCIad of PCIad is

component ALT_PLL

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

begin

ALT_PLL_inst : ALT_PLL PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

end archPCIad;

It looks like you are figuring it out.

You can of course change the *_sig names and the ALT_PLL_inst name to be anything you want. The MegaWizard _inst.vhd file used these as placeholders for the names of your choice.

you can avoid copying the component declaration alltogether, by doing direct instantiation:

library ieee;

use ieee.std_logic_1164.all;

entity PCIad is port(

areset_sig: in STD_LOGIC;

inclk0_sig: in STD_LOGIC;

c0_sig: out STD_LOGIC;

locked_sig: out STD_LOGIC

);

end PCIad;

architecture archPCIad of PCIad is

begin

ALT_PLL_inst : entity work.ALT_PLL --this is the direct bit

PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

end archPCIad;

Again, you can even avoid using the wizard by using the altera_mf library. It gives me more direct control, and less extra rubbish/wrappers cluttering up my working directory (though I know some people prefer setting stuff up via the wizard):

library altera_mf;

use altera_mf.altera_mf_components.all;

.....

--this comes from the altera_mf library

ALT_PLL_inst : altpll

generic map (

OPERATION_MODE => "NORMAL",

.....

)

PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

all of the generics can be found via help -> megafunctions/lpm.

--- Quote Start ---

Again, you can even avoid using the wizard by using the altera_mf library. It gives me more direct control, and less extra rubbish/wrappers cluttering up my working directory (though I know some people prefer setting stuff up via the wizard)

...

all of the generics can be found via help -> megafunctions/lpm.

--- Quote End ---

Be aware that the altera_mf library is functional simulation models. It is not intended for synthesis.

The MegaWizard has the advantage of preventing some illegal combinations of parameter settings. If you choose to instantiate megafunctions directly instead of using a MegaWizard variation file, you can still create a MegaWizard variation file to get a correct set of parameters/generics that you can copy to your own file where you are instantiating the megafunction like altpll directly. If you don't use the MegaWizard at all, then see the on-line help page for the megafunction as Tricky mentioned or see the user guide for it at http://www.altera.com/literature/lit-ip.jsp to see what the available ports and parameters/generics are.