VHDL and Megafunctions

you can avoid copying the component declaration alltogether, by doing direct instantiation:

library ieee;

use ieee.std_logic_1164.all;

entity PCIad is port(

areset_sig: in STD_LOGIC;

inclk0_sig: in STD_LOGIC;

c0_sig: out STD_LOGIC;

locked_sig: out STD_LOGIC

);

end PCIad;

architecture archPCIad of PCIad is

begin

ALT_PLL_inst : entity work.ALT_PLL --this is the direct bit

PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

end archPCIad;

Again, you can even avoid using the wizard by using the altera_mf library. It gives me more direct control, and less extra rubbish/wrappers cluttering up my working directory (though I know some people prefer setting stuff up via the wizard):

library altera_mf;

use altera_mf.altera_mf_components.all;

.....

--this comes from the altera_mf library

ALT_PLL_inst : altpll

generic map (

OPERATION_MODE => "NORMAL",

.....

)

PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

all of the generics can be found via help -> megafunctions/lpm.