VHDL and Megafunctions

Thank you for responding.

At the bottom are the three files the the wizard generated. Where should

they be placed. Sorry for being lame but I have still not got this to work.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity PCIad is port(

);

end PCIad;

architecture archPCIad of PCIad is

begin

end archPCIad;

-------------------------------------------------------

component ALT_PLL

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

--------------------------------------------------------

FUNCTION ALT_PLL (areset, inclk0)

RETURNS (c0, locked);

--------------------------------------------------------

ALT_PLL_inst : ALT_PLL PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

--------------------------------------------------------