VHDL and Megafunctions

It should look like this

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity PCIad is port(

areset_sig: in STD_LOGIC;

inclk0_sig: in STD_LOGIC;

c0_sig: out STD_LOGIC;

locked_sig: out STD_LOGIC

);

end PCIad;

architecture archPCIad of PCIad is

component ALT_PLL

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

begin

ALT_PLL_inst : ALT_PLL PORT MAP (

areset => areset_sig,

inclk0 => inclk0_sig,

c0 => c0_sig,

locked => locked_sig

);

end archPCIad;