verilog task passing values

Question

In verilog ,I have doubt while passing different values of one argument to task

eg:-

module sample_ref(input wire clkA, rstA ,SA, output wire d);

initial

begin

repeat(6)

@(posedge clkA)# 1;

operation(rstA,SA);

end

task operation(input wire rst, s);

begin

if(rst)

$display("@%0t test1",$time);

else if(s)

$display("@%0t test2",$time);

end

endtask

endmodule

// here when I try to pass values of variable SA to s inside the task at different times(not at initial time), it didn't enter in to the task. Please explain these..

altera_forum · Answer

Without the other code that doesn't work, is impossible to comment on what might be wrong

altera_forum · Answer

A task cannot have a wire as an argument

altera_forum · Answer

An initial statement cannot have an always block.

altera_forum · Answer

--- Quote Start ---  An initial statement cannot have an always block.  --- Quote End ---    Where is there an always block?

altera_forum · Answer

actually I'm verifying(using Verilog) a DUT by using reference model in that I have doubt on pass arguments to the task inside if else statement.

initial

begin

repeat(6)

@(posedge clkA)# 1;

operation(rstA,SA);

end

task operation(input rst, s);

begin

if(rst)

$display("@%0t test1",$time);

else if(s)

$display("@%0t test2",$time);

end

endtask

here when I try to pass values of variable SA to s inside the task at different times(not at initial time), it didn't enter in to the task. Please explain these

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verilog task passing values

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