verilog task passing values

actually I'm verifying(using Verilog) a DUT by using reference model in that I have doubt on pass arguments to the task inside if else statement.

initial

begin

repeat(6)

@(posedge clkA)# 1;

operation(rstA,SA);

end

task operation(input rst, s);

begin

if(rst)

$display("@%0t test1",$time);

else if(s)

$display("@%0t test2",$time);

end

endtask

here when I try to pass values of variable SA to s inside the task at different times(not at initial time), it didn't enter in to the task. Please explain these