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Honored Contributor
Honored Contributorverilog task passing values
In verilog ,I have doubt while passing different values of one argument to task eg:- module sample_ref(input wire clkA, rstA ,SA, output wire d); initial begin repeat(6) @(posedg...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- An initial statement cannot have an always block. --- Quote End --- Where is there an always block?
