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Altera_Forum
Honored Contributor
Honored Contributorverilog task passing values
In verilog ,I have doubt while passing different values of one argument to task eg:- module sample_ref(input wire clkA, rstA ,SA, output wire d); initial begin repeat(6) @(posedg...
Altera_ForumHonored Contributor
Honored ContributorInstead of just repeating your question from the first post - how about showing us some code that exhibits the problems?
