Verilog Syntax Error

wrong:

if ( C == 1'b0 && C == 1'b0);
O = d

right:

if ( C == 1'b0 && C == 1'b0)
O = d;

OK:

1. I have implemented FvM's changes.

2. kaz, when I try and delete the "endmodule" at the end of module codes (line 14), compilation errors tell me that it is required. So I have kept that there.

3. however, i don't think anybody has yet told me why i am persistently getting this error:

Error (10170): Verilog HDL syntax error at de1sign.v(16) near text "begin"; expecting a description

If anybody at all could clarify this error for me, and tell me how to solve it, it would be greatly appreciated.

insert always before begin

However you have other errors and it will help you to follow some templates.

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However, I don't think anybody has yet told me why I am persistently getting this error

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In simple words, because you're permanently ignoring Verilog syntax rules. :(

See below a version that compiles without errors.

module de1sign (C, SW);
input  SW;
output  C;
assign C = SW;
assign C = SW;
endmodule
module codes (O, C, d, e, i) ; //possibility of using "i" if "1" is reserved.
input  C;
output d;
output e;
output i;
output reg O;
always @ (*)
begin  
if ( C == 1'b0 && C == 1'b0) // wrongly placed semicolon removed
O = d;
if ( C == 1'b0 && C == 1'b1) // wrongly placed semicolon removed
O = e;
if ( C == 1'b1 && C == 1'b0) // wrongly placed semicolon removed
O = i;
end
endmodule
module hexcircuit (O, HEX0, d, e, i);
input O;
input d;
input e;
input i;
output reg  HEX0;
always @ (O) // wrongly placed semicolon removed
begin
if ( O == d )
HEX0 = 7'b100_0010;
if ( O == e )
HEX0 = 7'b011_0000;
if ( O == i )
HEX0 = 7'b100_1111;
end
endmodule

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In simple words, because you're permanently ignoring Verilog syntax rules. :(

See below a version that compiles without errors.

(FIXED CODE)

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Hi FvM,

Thank you, I had just realized what I was doing wrong in terms of syntax rules. :huh:

However, now I have to sort out all the logic errors. :(

Once compiled and fed into my board, it does not do ANYTHING.

If you haven't figured out already, I am supposed to toggle switches 0-2, and use them to display d,e,1 in turn on HEX0 display.

Any ideas on what may be wrong?

Thanks again for the help.

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However, now I have to sort out all the logic errors.

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Right, I ignored reasonable logic up to now. Your design has 4 unrelated modules. I would expect a top entity linking the four. I presume, that you basically understand the operation of a hierachical design.

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always @ (*)

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Just curiosity, what is this ? The conventional way to write is:

always @ (C or d or e or i)

Is always @(*) equivalent to that? Is this a new syntax added in Verilog to write sensitivity list briefly?