Verilog Syntax Error

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However, I don't think anybody has yet told me why I am persistently getting this error

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In simple words, because you're permanently ignoring Verilog syntax rules. :(

See below a version that compiles without errors.

module de1sign (C, SW);
input  SW;
output  C;
assign C = SW;
assign C = SW;
endmodule
module codes (O, C, d, e, i) ; //possibility of using "i" if "1" is reserved.
input  C;
output d;
output e;
output i;
output reg O;
always @ (*)
begin  
if ( C == 1'b0 && C == 1'b0) // wrongly placed semicolon removed
O = d;
if ( C == 1'b0 && C == 1'b1) // wrongly placed semicolon removed
O = e;
if ( C == 1'b1 && C == 1'b0) // wrongly placed semicolon removed
O = i;
end
endmodule
module hexcircuit (O, HEX0, d, e, i);
input O;
input d;
input e;
input i;
output reg  HEX0;
always @ (O) // wrongly placed semicolon removed
begin
if ( O == d )
HEX0 = 7'b100_0010;
if ( O == e )
HEX0 = 7'b011_0000;
if ( O == i )
HEX0 = 7'b100_1111;
end
endmodule