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Altera_Forum
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14 years ago

Verilog Syntax Error

module de1sign (C, SW); input SW; output C; assign C = SW; assign C = SW; endmodule module codes (O, C, d, e, i) ; //possibility of using "i" if "1" is reserved. input C; output d; output e; out...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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In simple words, because you're permanently ignoring Verilog syntax rules. :(

See below a version that compiles without errors. 

(FIXED CODE)

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Hi FvM,

Thank you, I had just realized what I was doing wrong in terms of syntax rules. :huh:

However, now I have to sort out all the logic errors. :(

Once compiled and fed into my board, it does not do ANYTHING.

If you haven't figured out already, I am supposed to toggle switches 0-2, and use them to display d,e,1 in turn on HEX0 display.

Any ideas on what may be wrong?

Thanks again for the help.