hi all... currently working on a project, i have a top level module (module A), with a module instantiated in it ,module B. I just have one question. When does the system know when to start running module B ? in module A, i have all the input to module B declared and assigned. However, at certain point of the codes, where there are supposed to have output from module B, the system just seems not running module B. When i simulated using modelsim, all the variables in module B are 'x'. any clue why is this happening ? or did i make any mistakes anywhere ? please advice...thanks... p/s: sorry if i make my question complicated...i am still new to verilog...:confused:

Everytime I've done that, it's because I forgot to drive something into the module, it became unknown and propogated around. You said you're driving everything, but maybe worth a double-check. I think modelsim has a tracex capability, where you can trace an x back to where it came from. I only used it once and struggled to figure it out(I have very little modelsim experience), so maybe someone else can post more details?

ya, confirmed that i drive all the inputs into the module. i thought that if we drive all the necessary inputs to the module, it should start operating and come up with an output...no ?

Is the output dependent on something that might not be initialized like a flip flop or RAM in module B? Also I would double check signal widths in both modules to make sure signals are not getting truncated somewhere in your logic. I'm not sure if there is a way to check for this in Modelsim but the Quartus II synthesis engine should issue you a warning when this happens.

--- Quote Start --- Is the output dependent on something that might not be initialized like a flip flop or RAM in module B? --- Quote End --- sorry, but i don't really understand this question. There is output from module B that i need in module A. perhaps i will just provide you guys with parts of the code to make things clear. module A; reg s, sq, sqe; reg q; reg s_length, q_length, sqe_length; reg subset_start; wire subset_out,subset_done; B mod_B(q,q_length,sqe,sqe_length,subset_start,subset_out,subset_done); always @* begin subset_start=0; cS=3'd 1; s=s_in; s_length=5'd 1; q=s_in; q_length=5'd 1; sq={s,q}; sqe=sq>>1; sqe_length=s_length+q_length-1; subset_start=1; (some codes here) case (subset_out) 1: begin . . . (some codes here) end 0:begin . . . (some codes here) end end endmodule module B(q,q_length,sqe,sqe_length,start,out,done); input start; input q_length; input q; input sqe; input sqe_length; output reg out,done; always @ (posedge start) begin . . . (codes) end endmodule as you can see, i had initialized every input to module B. i'm just wondering why i can't get any output out of it. Module B wasn't executing where it should be. the variable "subset_start" in module A was used to trigger the always block in module B. Can i do something like this ? Or i did it in the wrong way ?

I meant initialize registers/RAMs in the submodule. I see in module B you have some sort of net with sensitivity to 'start' but without seeing that net I have no clue what you have implemented. If your intent was to create a flipflop you should be driving it with a clock and reset as well and using an enable bit if you don't want it to capture every clock cycle. If you don't drive a reset into a register at the beginning of the simulation you'll get unknown data out of it (Modelsim can't assume high or low outputs from unitialized regs/RAMs). There are templates in Quartus II under the edit menu you can take a look at for typical hardware blocks such as registers, memory, etc...

verilog-module instantiation | Altera Community

15 Replies

Altera_Forum
Honored Contributor
14 years ago
ok...then how am i going to control when to execute the submodule ?
Altera_Forum
Honored Contributor
14 years ago
Modules are instantiated in concurrent code and unconditionally "executed".
Altera_Forum
Honored Contributor
14 years ago
is it possible to make it "contidionally" ?
Altera_Forum
Honored Contributor
14 years ago
Your module contains only combinational logic. How do you want to make it conditional? A clocked module can be designed conditional with a clock enable.
Altera_Forum
Honored Contributor
14 years ago
I highly recommend you copy the entire submodule into the post. You put "codes here" which leaves us guessing what you have coded in there making it difficult to give you suggestions of what might not be driven/initialized.

Here is an example of what FvM and I are talking about:

always @ (posedge clk)
begin
if (enable)
my_register <= input_data;
end

In that simple code fragment I have a register that captures input_data when enable is high. What is missing is the reset condition so until the enable signal is driven high 'my_register' will drive out unknown contents if I were to simulate this.

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verilog-module instantiation

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