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Altera_Forum's avatar
Altera_Forum
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14 years ago

verilog-module instantiation

hi all... currently working on a project, i have a top level module (module A), with a module instantiated in it ,module B. I just have one question. When does the system know when to start running m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Your module contains only combinational logic. How do you want to make it conditional? A clocked module can be designed conditional with a clock enable.