verilog-module instantiation

I highly recommend you copy the entire submodule into the post. You put "codes here" which leaves us guessing what you have coded in there making it difficult to give you suggestions of what might not be driven/initialized.

Here is an example of what FvM and I are talking about:

always @ (posedge clk)

begin

if (enable)

my_register <= input_data;

end

In that simple code fragment I have a register that captures input_data when enable is high. What is missing is the reset condition so until the enable signal is driven high 'my_register' will drive out unknown contents if I were to simulate this.