Altera_Forum
Honored Contributor
9 years agoVerilog $display(" ") equivalent/does not compile in VHDL ?
Hello,
I have been looking for the equivalent of the $display("") command in VHDL for some time now: main_clock: process begin CLK_CPU<='1'; wait for TClock/2; $display("test "); --errorCLK_CPU<='0'; wait for TClock/2; end process; What ever i do the lines above do not compile. (see bold) ** Error: C:/FpgaProjects/Q17/DE2_115_Shark_Serial_Component/main_bench.vhd(33): near "$": syntax error Should i include a library or is there a modelsim setting i need to change ? Lots of documents are available about the different possible parameters and Modelsim tutorials, the answer to this rather basic question i could not find. Thanks for any help, Johi.