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Altera_Forum
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8 years ago

Verilog $display(" ") equivalent/does not compile in VHDL ?

Hello, I have been looking for the equivalent of the $display("") command in VHDL for some time now: main_clock: process begin CLK_CPU<='1'; wait for TClock/2; $displa...
Altera_Forum's avatar
Altera_Forum
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8 years ago

You cannot use Verilog/SV system tasks in VHDL. Both are different languages. In VHDL you can use the write () function to write values to console during simulation. Use the IEEE textio package and then call the write ( ) function. 


Use Std.textio.all;
..
..
write ( ) ; -- write values to display