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Altera_Forum's avatar
Altera_Forum
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8 years ago

Verilog $display(" ") equivalent/does not compile in VHDL ?

Hello, I have been looking for the equivalent of the $display("") command in VHDL for some time now: main_clock: process begin CLK_CPU<='1'; wait for TClock/2; $displa...
Altera_Forum's avatar
Altera_Forum
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8 years ago

There are really two answers to this. You can either use the report statement:

report "test";

or you can use the textio library. 


use std.textio.all;
....
write(OUTPUT, "test" & LF);  -- test and line-feed

OUTPUT is a built in file that is the system console. There are many tutorials out there on how to use textio.

VHDL does not have equivolents of the Verilog System Calls (that start with $).