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Altera_Forum
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8 years ago

Verilog $display(" ") equivalent/does not compile in VHDL ?

Hello, I have been looking for the equivalent of the $display("") command in VHDL for some time now: main_clock: process begin CLK_CPU<='1'; wait for TClock/2; $displa...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hello Tricky & eapenabrm,

Tanks for the answer, I read about write & textio, thought this was reserved for disk file io.

Never thought about the OUTPUT stream.

Best Regards,

Johi.