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Altera_Forum's avatar
Altera_Forum
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8 years ago

Verilog coding

Hi all,

I am just start to learn Verilog and immediately had a problem - please take a look at code - why "repeat (10) does not working?

I was expected a 5 pulse train at every oop pulse - but in simulation the is no changes of pls output at all.

I tried to use for and while condition - same result - no pulse train.

///////////////////////////////////////////////////////////////////////////////////////////////////

module buff_gen (oop,pls);

input oop;

wire oop;

output pls;

reg pls;

initial begin pls = 0; end

always @ (posedge oop)

begin

repeat (10)

begin

# 5 pls = ~pls;

end

end

endmodule

////////////////////////////////////////

please tell me what I am doing wrong.

thanks

cicga

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    did you input a rising edge on oop?

    And what are you simulating? RTL or netlist? repeat is not a synthesisable construct and is for simulation only.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    If you're trying to simulate this, you need to have an input stimulus for oop to make it work at all. Otherwise, pls will just stay low. And as Tricky mentioned, the repeat construct is not synthesizable if you're trying to make this work in hardware.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Thanks for help,

    1. Where I can find specs for Verilog used in Quartus 2 and its specs - what can be used for simulation only etc.

    2. Yes I am sending oop signal ,but a problem is that not only repeat() don't work but nether for() and while():

    module buff_gen (oop,pls);

    input oop;

    wire oop;

    output pls;

    reg pls;

    integer i;

    initial begin pls = 0; end

    always @ (posedge oop) begin

    for (i=0;i<10;i=i+1)

    begin

    pls = ~pls;

    end

    end

    endmodule

    please check attachment with waveform pictures.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    1. Try the HDL coding styles from the quartus handbook: https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf

    2. That is the quartus simulator. It only supports netlist simulation which will require synthesis. If you check the warnings, you'll probably find some code has been ignored. Also note that# N statements are also ignored for syntheis.

    Loops can only be used for parallel circuits. Not for events that occur in time. You need to build the circuit for that purpose, probably with a counter.