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Altera_Forum's avatar
Altera_Forum
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8 years ago

Verilog coding

Hi all, I am just start to learn Verilog and immediately had a problem - please take a look at code - why "repeat (10) does not working? I was expected a 5 pulse train at every oop pulse - ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

did you input a rising edge on oop?

And what are you simulating? RTL or netlist? repeat is not a synthesisable construct and is for simulation only.