Verilog coding

Thanks for help,

1. Where I can find specs for Verilog used in Quartus 2 and its specs - what can be used for simulation only etc.

2. Yes I am sending oop signal ,but a problem is that not only repeat() don't work but nether for() and while():

module buff_gen (oop,pls);

input oop;

wire oop;

output pls;

reg pls;

integer i;

initial begin pls = 0; end

always @ (posedge oop) begin

for (i=0;i<10;i=i+1)

begin

pls = ~pls;

end

end

endmodule

please check attachment with waveform pictures.