Verilog coding

1. Try the HDL coding styles from the quartus handbook: https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf

2. That is the quartus simulator. It only supports netlist simulation which will require synthesis. If you check the warnings, you'll probably find some code has been ignored. Also note that# N statements are also ignored for syntheis.

Loops can only be used for parallel circuits. Not for events that occur in time. You need to build the circuit for that purpose, probably with a counter.