verilog code for counter which counts in both positive and neg ede clock

Well, you might struggle in an FPGA, as FPGAs can only use either the rising or the falling, not both.

it can be do with some trick;

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;
entity posnegcounter is
  generic(
    WIDTH_COUNT : natural := 8
  );
  port(
    Clk     : in  std_logic;
    Reset   : in  std_logic;
    Counter : out std_logic_vector(WIDTH_COUNT - 1 downto 0)
  );
end entity posnegcounter;
architecture arch of posnegcounter is
  signal poscount : unsigned(WIDTH_COUNT - 2 downto 0); -- only need count half
  signal negcount : unsigned(WIDTH_COUNT - 2 downto 0);
begin
  process(Clk , Reset)
  begin
      if (reset = '1') then
        poscount <= to_unsigned(0, WIDTH_COUNT - 1) ;
        negcount <= to_unsigned(0, WIDTH_COUNT - 1) ;
      elsif rising_edge(Clk) then
        poscount <= poscount + 1;
      elsif falling_edge(Clk) then
        negcount <= negcount + 1;
      end if;
    end process;
  counter <= std_logic_vector(poscount + negcount);
end arch;

Add two on every positive edge and assume odd when sampled on a negative edge (or v.v.).

Or generate a 2x clock...

At what time would you sample the counter, and using which clock? You could do something like:

reg  cnt_q;
always_ff @(posedge clk)
  cnt_q <= cnt_q + 31'd1;
   
reg lsb_q;
always_ff @(negede clk)
  lsb_q <= ~lsb_q;
wire  counter = {cnt_q, lsb_q};