Altera_ForumHonored Contributor12 years agoverilog code for counter which counts in both positive and neg ede clock Hi, Anyone please help me write a counter module in verilog in which count should be incremented in both positive edge and negaive edge clock.... please help... Thank YouShow More
Altera_ForumHonored Contributor12 years agoAdd two on every positive edge and assume odd when sampled on a negative edge (or v.v.).
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