verilog code for counter which counts in both positive and neg ede clock

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Well, you might struggle in an FPGA, as FPGAs can only use either the rising or the falling, not both.

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That's not exactly true. You can use both positive and negative edges but not to toggle the same register.

I don't do Verilog, but in VHDL it may look like this:

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;
entity posnegcounter is
  generic(
    WIDTH_COUNT : natural := 8
  );
  port(
    Clk     : in  std_logic;
    Reset   : in  std_logic;
    Counter : out std_logic_vector(WIDTH_COUNT - 1 downto 0)
  );
end entity posnegcounter;
architecture arch of posnegcounter is
  signal poscount : unsigned(WIDTH_COUNT - 2 downto 0); -- only need count half
  signal negcount : unsigned(WIDTH_COUNT - 2 downto 0);
begin
  process(Clk , Reset)
  begin
      if (reset = '1') then
        poscount <= to_unsigned(0, WIDTH_COUNT - 1) ;
        negcount <= to_unsigned(0, WIDTH_COUNT - 1) ;
      elsif rising_edge(Clk) then
        poscount <= poscount + 1;
      elsif falling_edge(Clk) then
        negcount <= negcount + 1;
      end if;
    end process;
  counter <= std_logic_vector(poscount + negcount);
end arch;

But still I wonder what the purpose might be?