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Altera_Forum
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11 years ago

verilog code for counter which counts in both positive and neg ede clock

Hi, Anyone please help me write a counter module in verilog in which count should be incremented in both positive edge and negaive edge clock.... please help... Thank You
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

At what time would you sample the counter, and using which clock? You could do something like: 

reg  cnt_q;
always_ff @(posedge clk)
  cnt_q <= cnt_q + 31'd1;
   
reg lsb_q;
always_ff @(negede clk)
  lsb_q <= ~lsb_q;
wire  counter = {cnt_q, lsb_q};