Honored ContributorHi,
I need to implement multi-port memories for stratix series for my thesis work. If anybody could suggest/give sample verilog codes to implement bram it will be of great help to me. I am having trouble to start off without the building block. :( Thanks.
Honored ContributorYou have two choices[list][*]Use the megawizard to implement your memory block (in the Tools menu). It can create a Verilog block that instantiates Altera primitives. You can configure a lot of options but the generated code will only work with Quartus[*]make a table that will be recognized as a memory block by the synthesizer. It is a bit harder to code, but it is more portable and should also work with other tools from other FPGA manufacturers. Have a look at pages 13-13 and over of this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) to see how you can write your code to have it recognized as a memory block.[/list]
Honored ContributorHi,
Thanks a lot for your reply Daixiwen. I used the megawizard to implement the memory block. I included the altera_mf.v file as will along with the generated 2 port RAM .v file. However when I compile the project it is throwing 2 errors : 1. Error (10207): Verilog HDL error at altera_mf.v(44589): can't resolve reference to object "FEATURE_FAMILY_ARRIAV" --- Why is it referring to ARRIAV family when I am not using it?? 2. Error (12152): Can't elaborate user hierarchy "altsyncram:altsyncram_component" --- And order of the .v files is: 1st altera_mf.v and then the generated 2 port RAM .v file. Since altera_mf.v in compiled 1st why is it not able to elaborate altsyncram_component? I am in the process of learning QuartusII tool. Any kind of help will be of great help to me. Thanks.Honored ContributorYou don't need to add the altera_mf.v file to your project, IIRC it is only needed for simulation.
Did you have your project open in Quartus before you called the megawizard, and was the project set with the correct FPGA target? IIRC the megawizard uses the project's FPGA type by default (but you can change it).Honored ContributorDaixiwen , as you said we do not need the altera_mf.v file in the project. I could compile it successfully :)
Honored ContributorI just needed to confirm what I am doing is correct wrt writing a verilog code for RAM and initialising its memory contents. I am having no luck even after following these steps:
1. .v file for a dual port RAM according to Recommended HDL Coding Styles. 2. Have added this attribute : (* ram_init_file = "my_memory_blocks.hex" *) reg [7:0] mem [255:0]; 3. I have changed the path of convert_hex2ver.dll in the modelsim.ini file : Veriuser = C:\altera\11.1\modelsim_ase\win32aloem\convert_hex2ver.dll 4. All the design files and the .hex file are in my project folder. I am not gettin any output when I am trying to read from the memory :( . It would be of great help to me if somebody could tell me if I am going wrong somewhere. Looking forward for a reply. Thanks.Honored ContributorHave you looked at the templates yet built into Quartus? With a verilog file open go to Edit --> Insert Template --> Verilog HDL --> Full Designs --> RAMs and ROMs There are a bunch of different RAM and ROM implementations that show you how to structure your code and pre-initialize the memory block. You can use the verilog $readmemb command to pull in the initialization contents from a file.
