Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Verilog code for bram

Hi, I need to implement multi-port memories for stratix series for my thesis work. If anybody could suggest/give sample verilog codes to implement bram it will be of great help to me. I am havi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Have you looked at the templates yet built into Quartus? With a verilog file open go to Edit --> Insert Template --> Verilog HDL --> Full Designs --> RAMs and ROMs There are a bunch of different RAM and ROM implementations that show you how to structure your code and pre-initialize the memory block. You can use the verilog $readmemb command to pull in the initialization contents from a file.