Verilog code for bram

Hi,

Thanks a lot for your reply Daixiwen. I used the megawizard to implement the memory block. I included the altera_mf.v file as will along with the generated 2 port RAM .v file. However when I compile the project it is throwing 2 errors :

1. Error (10207): Verilog HDL error at altera_mf.v(44589): can't resolve reference to object "FEATURE_FAMILY_ARRIAV" --- Why is it referring to ARRIAV family when I am not using it??

2. Error (12152): Can't elaborate user hierarchy "altsyncram:altsyncram_component" --- And order of the .v files is: 1st altera_mf.v and then the generated 2 port RAM .v file. Since altera_mf.v in compiled 1st why is it not able to elaborate altsyncram_component?

I am in the process of learning QuartusII tool. Any kind of help will be of great help to me.

Thanks.