Honored ContributorHi, this is a simple counter with asynch pre-set(not wired in diagram), enable, load and synch add +1. i can't figure the trick to get rid of one extra mux column and use the FF enable (where red arrow is). Do you have any ideas please?
cheers. Pretty sure there's a way to do it....
Honored ContributorWithout the code - it is difficult to tell what to do to fix it.
Honored Contributorsomething like this, though i tried different combinations for the 'if' condition, as in in different places or using 'elseif', yet still same result...
process(clk, rst) variable cnt : unsigned(3 downto 0) begin if rst = '0' then cnt := (others => '1'); elsif rising_edge(clk) then if load = '1' then cnt := new_data; end if; if ena = '1' then cnt := cnt +1; end if; end if; cnt_out <= cnt; end process;Honored Contributorthats because your enable isnt acting as an enable. cnt_out is a combinatorial version of cnt+1 or cnt, using the enable bit to select. This is because you used a variable for cnt, and then assigned it to a signal after you've done +1
The fix : remove the variable complelely and use signals instead. Switch to vhdl 2008 and replace cnt with cnt_out. Variables can cause these issues as the ordering of the code can affect the circuit. If you used only signals, then you probably wouldnt have had this problem.Honored Contributorthanks tricky. i tried with signals too, still same issue. may be the vhdl version. i shall try again and post what happened. does it make much difference wheatear the FF ena is used or like in this case, going to a set of muxes? i'm kinda obsessed with making logic efficient and using least as possible, but some times not sure if it a good thing to do or not.
Honored ContributorHonored Contributori'll have a look kaz. i just wrote the code snippet quickly as i don’t have quartus available at the moment. shall check tonight and post.... thanks for supporting too, great people
Honored ContributorI fixed it :). super. this is what made me realize :
--- Quote Start --- thats because your enable isnt acting as an enable. cnt_out is a combinatorial version of cnt+1 or cnt, using the enable bit to select. --- Quote End --- it works both with signals and variables, have a look : process(clk, rst)
variable sig_pc : unsigned(n downto 0);
begin
if rst = '0' then
sig_pc := (others => '1');
elsif falling_edge(clk) then
if pc_en = '1' then
sig_pc := sig_pc +1;
if pc_ld = '1' then
sig_pc := unsigned(pc_new);
end if;
end if;
end if;
pc_out <= std_logic_vector(sig_pc);
end process;
