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Altera_Forum's avatar
Altera_Forum
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9 years ago

up counter needs fixing - confused . simple question

Hi, this is a simple counter with asynch pre-set(not wired in diagram), enable, load and synch add +1. i can't figure the trick to get rid of one extra mux column and use the FF enable (where red arr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

thanks tricky. i tried with signals too, still same issue. may be the vhdl version. i shall try again and post what happened. does it make much difference wheatear the FF ena is used or like in this case, going to a set of muxes? i'm kinda obsessed with making logic efficient and using least as possible, but some times not sure if it a good thing to do or not.