up counter needs fixing - confused . simple question

I fixed it :). super. this is what made me realize :

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thats because your enable isnt acting as an enable. cnt_out is a combinatorial version of cnt+1 or cnt, using the enable bit to select.

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it works both with signals and variables, have a look :

    process(clk, rst)
        variable sig_pc : unsigned(n downto 0);
    begin
        if rst = '0' then
            sig_pc := (others => '1');
        elsif falling_edge(clk) then
            if pc_en = '1' then
                sig_pc := sig_pc +1;
                if pc_ld = '1' then
                   sig_pc := unsigned(pc_new);
                end if;
                
            end if;
        end if;
        pc_out <= std_logic_vector(sig_pc);
    end process;

awesome. thanks all. great