up counter needs fixing - confused . simple question

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thanks tricky. i tried with signals too, still same issue. may be the vhdl version. i shall try again and post what happened. does it make much difference wheatear the FF ena is used or like in this case, going to a set of muxes? i'm kinda obsessed with making logic efficient and using least as possible, but some times not sure if it a good thing to do or not.

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one point: you statement

cnt_out <= cnt;

is outside clk edge but not in sensitivity list. simulation will not work