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thats because your enable isnt acting as an enable. cnt_out is a combinatorial version of cnt+1 or cnt, using the enable bit to select. This is because you used a variable for cnt, and then assigned it to a signal after you've done +1
The fix : remove the variable complelely and use signals instead. Switch to vhdl 2008 and replace cnt with cnt_out.
Variables can cause these issues as the ordering of the code can affect the circuit. If you used only signals, then you probably wouldnt have had this problem.
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Tricky, I am not sure you are right here.
cnt is used before assigning it to itself so a register should be generated for the variable. so enable should work and takes priority over load.
I know for sure such counters work with variables. Though I personally use variables very occasionally.
I think the problem may be in the last statement outside clk edge.
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