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Altera_Forum's avatar
Altera_Forum
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9 years ago

up counter needs fixing - confused . simple question

Hi, this is a simple counter with asynch pre-set(not wired in diagram), enable, load and synch add +1. i can't figure the trick to get rid of one extra mux column and use the FF enable (where red arr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

something like this, though i tried different combinations for the 'if' condition, as in in different places or using 'elseif', yet still same result...

process(clk, rst)

variable cnt : unsigned(3 downto 0)

begin

if rst = '0' then

cnt := (others => '1');

elsif rising_edge(clk) then

if load = '1' then

cnt := new_data;

end if;

if ena = '1' then

cnt := cnt +1;

end if;

end if;

cnt_out <= cnt;

end process;