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Altera_Forum's avatar
Altera_Forum
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16 years ago

Undeclared Parameter & Bus Range Problem

hi there,

i have another problem with a VHDL Code.

After including the VHDL in the project and generating a symbol, which i dropped on a bdf file, i want to start the analysis and elaboration to detect ports and so on.

There seems to be a problem with it, because if i start with the elaboration, there comes first up a Warning where it says "Warning: Undeclared parameter channelwidth/chancount" and after that i got an error "Error: Bus range for signal "port "I2S_DATA_I[2**channelwidth/chancount-1..0]" (ID I2S_Input_S:inst9)" must be a number"

I'm using Quartus II Version: 9.0 with SP 1

I'm very frantically because i've found only one thread with the same problem here and the solution there doesn't work on my project.

Hope anybode could help me!?

best regards

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It sounds like you havent given values for the generics "channelwidth" and "chancount" in the BDF file, and they dont have default values in the VHDL code.

    Try setting this on:

    view -> "show parameter assignments"

    Then a little box should be attached to the graphical instantiation of the VHDL files where you can set the generic values.

    Unfortunatly, if the VHDL has non-trivial generics, you cannot instantiate it from BDF unless you set default values in the VHDL code. But in this case, it looks like its just integers, which will be fine.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks Tricky for your reply!

    I've attached a photo for better understanding.

    As you can see this box with the parameter and its values is "on" so the values are set.

    Do you've got any other idea?

    Thanks alot!

    elec

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    you've named the input as "eas1_sdinb" as a single bit input. You need to give this the same width as the input to inst9.

    If thats not the problem, then Id move over to chaging this top level file to VHDL instead of BDF. Ive had problems generating schematics from VHDL before with port sizings and incorrect type casting.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I guess I have never tried to do more than a width-1 in a generic before. I would probably add a generic which is IN_DATA_WIDTH, then replace the port with to IN_DATA_WIDTH-1. Then in the code of the file maybe check to make sure IN_DATA_WIDTH = 2**channelwidth/chancount, and assert an error if it is not. That way you have a check to make sure everything is correct. I don't know if this is the best way to do it but it would most likely solve your current problem. Just my .02