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Altera_Forum's avatar
Altera_Forum
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16 years ago

Undeclared Parameter & Bus Range Problem

hi there, i have another problem with a VHDL Code. After including the VHDL in the project and generating a symbol, which i dropped on a bdf file, i want to start the analysis and elaborat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It sounds like you havent given values for the generics "channelwidth" and "chancount" in the BDF file, and they dont have default values in the VHDL code.

Try setting this on:

view -> "show parameter assignments"

Then a little box should be attached to the graphical instantiation of the VHDL files where you can set the generic values.

Unfortunatly, if the VHDL has non-trivial generics, you cannot instantiate it from BDF unless you set default values in the VHDL code. But in this case, it looks like its just integers, which will be fine.