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Altera_Forum's avatar
Altera_Forum
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16 years ago

Undeclared Parameter & Bus Range Problem

hi there, i have another problem with a VHDL Code. After including the VHDL in the project and generating a symbol, which i dropped on a bdf file, i want to start the analysis and elaborat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

you've named the input as "eas1_sdinb" as a single bit input. You need to give this the same width as the input to inst9.

If thats not the problem, then Id move over to chaging this top level file to VHDL instead of BDF. Ive had problems generating schematics from VHDL before with port sizings and incorrect type casting.