New ContributorUnavailable detection of clock edge stably
ENTITY For_V1 IS PORT(
SCLK_SLAVER : IN std_logic;
testpin : OUT std_logic
);
END For_V1;
ARCHITECTURE circuit OF For_V1 IS
signal clk : std_logic:=SCLK_SLAVER;
BEGIN
process(SCLK_SLAVER)
begin
if SCLK_SLAVER'event and SCLK_SLAVER = '1' then
clk <= not clk;
end if;
end process;
testpin <= clk;
END circuit;
I find clk pin is not able to catch rising edge of SCLK_SLAVER every time, I am so confused with it.
could anyone give me a suggestion for it to fix the problem?
clock rising time:60~90ns
clock frequency : 80K
Green lin is SCLK_SLAVER
orange line is testpin
SCLK from I2C or SPI are notoriously bad for using as clocks It is much better to treat SCLK as any other signal and sample it inside the FPGA with a much faster clock, and use the edge of SCLK as a clock enable for your other registers that also use a proper system clock.
