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RLou1
New Contributor
New ContributorUnavailable detection of clock edge stably
ENTITY For_V1 IS PORT( SCLK_SLAVER : IN std_logic; testpin : OUT std_logic ); END For_V1; ARCHITECTURE circuit OF For_V1 IS signal clk : std_logic:=SCLK_SLAVER; BEGIN process(SCLK_SLAVER...
SCLK from I2C or SPI are notoriously bad for using as clocks It is much better to treat SCLK as any other signal and sample it inside the FPGA with a much faster clock, and use the edge of SCLK as a clock enable for your other registers that also use a proper system clock.
Tricky
Occasional Contributor
Occasional ContributorWhere does SCLK_SLAVER come from? a crystal or PLL?
If it is a logic generated clock then it can be possible that it is effected by high skew and temperature variability.
What is clk meant to drive? IS it driving internal logic?
