Forum Discussion

Ashish_Pradhan's avatar
Ashish_Pradhan
Icon for New Contributor rankNew Contributor
10 months ago
Solved

Unable to view Platform Designer generated IP interface and internal signals in Questa Simulation.

Hello, I am trying to simulate a RTL design which contains a modular scatter gather DMA (stream to memory-map) IP generated by Quartus Prime Pro platform designer. - I am able to generate HDL fr...
Hdl
Platform
Simulation
  • ShengN_altera's avatar
    ShengN_altera
    10 months ago

    Hi,


    May I know do you have any further concern?


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
10 months ago

Hi,


Since there's a new post on the another problem. I'll reply in that post instead.


Thanks,

Regards,

Sheng