Forum Discussion

Ashish_Pradhan's avatar
Ashish_Pradhan
Icon for New Contributor rankNew Contributor
10 months ago
Solved

Unable to view Platform Designer generated IP interface and internal signals in Questa Simulation.

Hello, I am trying to simulate a RTL design which contains a modular scatter gather DMA (stream to memory-map) IP generated by Quartus Prime Pro platform designer. - I am able to generate HDL fr...
Hdl
Platform
Simulation
  • ShengN_altera's avatar
    ShengN_altera
    10 months ago

    Hi,


    May I know do you have any further concern?


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
10 months ago

Hi,


You may go to Questa sim tab -> right-click the instance -> Add to -> Wave -> All items in region and below


Thanks,

Regards,

Sheng


Ashish_Pradhan's avatar
Ashish_Pradhan
Icon for New Contributor rankNew Contributor
10 months ago

Hello Sheng,

Thanks for the reply. Actually my issue is I am unable to see any transition in those out put channels which I mentioned in the previous reply. I can see the channels (msgdma_0_mm_write_address, *_mm_write_write, *_mm_write_byteenable, *_mm_write_writedata, or *_csr_irq_irq) in the waveform window.

To brief the problem:

-I exported CSR, descriptor, st_srink, & mm_write channels. Configure CSR and Descriptor through test bench, & driving data through st_srink, which I can see in the waveform, but I do not see any transition in the msgDMA mm_write output channel.

So could you pls guide me where I am going wrong , and how should I'll able to transfer data in msgDMA in a stream to memory-map configuration ?

Thanks & Regards,

Ashish