Unable to view Platform Designer generated IP interface and internal signals in Questa Simulation.

Hello ShengN,

Thanks for your suggestion. I am able to simulate it now.

But I observe following problem:

I am trying to simulate an Avalon modular scatter gather DMA (msgdma_0) in Stream to memory map configuration.

I am trying to send descriptor info (providing write address in appropriate field as specified in the user guide, appropriate Byteenable,
& Driving "write" signal high from test bench to the DUT (i.e msgdma_0), through the descriptor channel (msgdma_0_descriptor_slave_write, *_descriptor_slave_writedata, *_descriptor_slave_byteenable).

I am also driving data and valid through "msgdma_0_st_srink_data", "msgdma_0_st_srink_valid" and feed to the DUT(msgdma_0), configured CSR field as per uer guide.

Simulation is running properly without any error, I can see all the test bench signals in the waveform as expected.

But I do not see any output coming out from the platform designer generated IP (msgdma_0) in their respective output ports such as (msgdma_0_mm_write_address, *_mm_write_write, *_mm_write_byteenable, *_mm_write_writedata, or *_csr_irq_irq).

Can you pls guide where I am going wrong ? or suggest how can I get the expected behavior of Avalon modular scatter gather DMA.

Thanks,

Ashish.