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Ashish_Pradhan's avatar
Ashish_Pradhan
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Unable to view Platform Designer generated IP interface and internal signals in Questa Simulation.

Hello, I am trying to simulate a RTL design which contains a modular scatter gather DMA (stream to memory-map) IP generated by Quartus Prime Pro platform designer. - I am able to generate HDL fr...
Hdl
Platform
Simulation
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    May I know do you have any further concern?


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


In Questa, you may go to Simulate -> Design Optimization -> Visibility -> Apply full visibility check screenshot:

Or add set USER_DEFINED_ELAB_OPTIONS -voptargs=+acc in run_msim_rtl_verilog.do file then re-execute the .do file


Thanks,

Regards,

Sheng