Unable to simulate Avalon Memory-Mapped Clock Crossing Bridge Intel FPGA IP

I have a simple Platform Design QSYS system where I instantiate a "Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP" - see attachment. My design is synthesized successfully. However, when I try to compile the design with Mentor Questa, I always get this error:

# ** Error (suppressible): /storage/tools/altera/cds/212/quartus/eda/sim_lib/mentor/tennm_atoms_ncrypt.sv(40): (vopt-2732) Module parameter 'width' not found for override.

I cannot tell what is the root cause here because the Intel library is encrypted.

Has anyone encountered this issue before?

I am using Quartus Pro 21.2. My design is targeting Agilex FPGA device. And I'm using Mentor Questa 2021.1.

I am able to narrow down to the clock crossing bridge IP being the cause of the error but I have no idea how to fix it.

A quick summary of my Platform Design QSYS system: I have an Avalon Memory-Mapped master interface running at CLKA and an Avalon Memory-Mapped slave interface running at CLKB. The master interface and slave interface have different address bit-width but the same data bit-width. So in my Platform Designer QSYS, I instantiate an "Avalon Memory Mapped Pipeline Bridge Intel FPGA IP" and an "Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP". I connect the above master interface to s0 interface of the pipeline bridge IP. Then I connect the m0 of the pipeline bridge to the s0 of the clock crossing bridge. And finally, I connect the m0 of the clock crossing bridge to the above slave interface. My hope is with this QSYS, I have an Avalon addressing decoding logic that works with different clock domains.