Forum Discussion

Khai's avatar
Khai
Icon for New Contributor rankNew Contributor
4 years ago

Unable to simulate Avalon Memory-Mapped Clock Crossing Bridge Intel FPGA IP

I have a simple Platform Design QSYS system where I instantiate a "Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP" - see attachment. My design is synthesized successfully. However, when I t...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Since there are no further update or concern for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.