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Khai's avatar
Khai
Icon for New Contributor rankNew Contributor
3 years ago

Unable to simulate Avalon Memory-Mapped Clock Crossing Bridge Intel FPGA IP

I have a simple Platform Design QSYS system where I instantiate a "Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP" - see attachment. My design is synthesized successfully. However, when I t...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

I create a simple testbench for the design you attached and I'm able to simulate the design properly with msim_setup.tcl in .../example/sim/mentor. Check out the .do file for waveform. The project file is attached below for your reference. I notice tennm_atoms_ncrypt.sv located in quartus file make sure quartus 21.2 pro is properly licensed. Or you can suppress the error by using vsim -suppress 2732. Hope it may help.

Quartus: version 21.2 Pro

Questa: starter edition 2021.2

*Agilex device family tested with no problem as well.

Best Regards

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.