Altera_Forum
Honored Contributor
11 years agoUnable to Make Symbol from VHDL File
Hello, I am getting the following error when trying to make a symbol:
Error (10017): Can't create symbol/include/instantiation/component file for entity "Hist_Eq" because port "T_eq" are not currently supported by the Quartus II symbol/include/instantiation/component file generator Error: Quartus II 64-Bit Create Symbol File was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 616 megabytes Error: Processing ended: Wed Mar 25 12:19:23 2015 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 I will uploaded my archived design. It is very simple.