Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Unable to Make Symbol from VHDL File

Hello, I am getting the following error when trying to make a symbol: Error (10017): Can't create symbol/include/instantiation/component file for entity "Hist_Eq" because port "T_eq" are not cu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Tricky,

HI, I'm looking at the package of the design:

package hist_pkg is

type hist_array is array(0 to 3, 0 to 3) of integer;

type h_vector is array(0 to 3) of integer;

end package;

If I change the integer to unsigned, the error message I get when trying to make a symbol is "object unsigned is not declared". Did you get it make a symbol?

Thanks,

joe